The disclosure relates generally to large cluster persistence during placement optimization of integrated circuit designs.
By virtue of technology constraints, a nature of a netlist, and/or a design-style, integrated circuit designs typically contain a large cluster or group of elements (logical hierarchies in standard-cells, IP blocks, etc.,) that share a certain characteristic. In contemporary implementations of circuit placements, compact placement of such large clusters during the physical implementation of the logical netlist is under-emphasized or ignored due to the multi-objective (e.g., cell density, congestion, timing, etc.,) nature of circuit placement. In turn, contemporary implementations provide sub-optimal quality of results through inferior clustering itself and inferior handling of such large clusters during placement.